Yen-Chieh Kevin Huang

Global Talent in Semiconductor

Biography

Experiences

Accomplishments

Publications


Biography

Technical Manager, Foundry

QR, tsmc

2008 ~ 2020

QR Manager,

Design House

Supply Chain, Nordic Semiconductor

2020 ~ 2022

Engineering Director,

Design House

Supply Chain,

Nordic Semiconductor

2022 ~ 2023

Technical Advisor, GaN Metrology

Device Dynamics Lab

since 2023

Bechelor, Physics

National Tsinhua University

Graduated in 2000.

Master, Physics

National Taiwan University

Graduated in 2006 after serving the Army.

IEEE

Senior Member

since 2023

Business

Chartered Financial Analyst

Completed all three levels of CFA program.


Experiences

A Multidisciplinary Expert

Depending on the situation, I can either delve deeply into specific areas or provide a comprehensive overview.

Engineering

  • 3 yrs at design house Nordic Semiconductor.
  • 12 yrs at foundry tsmc.
  • 2 yrs at DRAM Nanya Tech.

Project Management

  • Engineering Director, 1yr at Nordic Semiconductor.
  • Product Qualification Manager, 2yrs at Nordic Semiconductor.
  • Technical Project Manager, 6 yrs at tsmc.

Research

  • 15 IEEE papers, 2 US patents.
  • ~130 citations.
  • GaN reliability metrology advisor at a start-up, DDL.

Accomplishments

01. Top Customer Satisfication

Based on customer satisfaction survey in 2020 and 2021: Quality and Reliability is the No.1 reason that customers choose Nordic products.

06. Methodology Bring-up

Provided statistical formula and stress test method of bit failure rate prediction of NVM IPs.

05. Innovation
  1. Tape-out world's first NBTI characterization test structure with sub-microsecond recovery time.
  2. Won the top prize of tsmc Q&R Idea Forum in 2012
02. Relentless Execution of Cross-Functional Projects

Planned and executed TSMC in-house foundation IP AEC-Q100 qualification of N16FFC automotive platform.

03. Risk Management

Negotiating reduced yet reasonable eFuse read spec

with all major customers. Roll out schedule of TSMC N28HP technology was not impacted..

04. Efficiency Improvement

Designed test arrays with decoder for in-parallel stress, boost TDDB throughput more than 10x.


Publications

IC and Transistor Reliability: Test Structure Design and Methodology

>120 citations

IEEE Papers

IEDM x1
IRPS x11
IIRW x3

Patents

USA x2

SOME OF MY

Referrals

"I am pleased to endorse Kevin's engineering expertise and research capabilities in IC reliability."

Director (Retired)

"Kevin's work ethic especially in risk management and data integrity meet our rigorous expectations."

Technologist

"I am more than happy to endorse Kevin's team development efforts and leadership."

Technical Manager

"I am pleased to endorse Kevin's expertise in IC reliability and his adaptability in diverse work environments."

Technical Lead

"As a program manager, Kevin is open-minded and maintains an unbiased stance. He makes decisions and takes action based on customer input and data."

Ray Chang

Program Manager

"I am delighted to endorse Kevin's innovative work in reliability test structure design."

Wayne Wang

RD Senior Manager

Get in touch

iam@kevinhuang.tw